#!/bin/sh -e ## 154_e500_mask.dpatch by Sebastian A. Siewior ## ## All lines beginning with `## DP:' are a description of the patch. ## DP: From 56093a7c7a72f478f04fcaa975b8f0bb428ea51e Mon Sep 17 00:00:00 2001 ## DP: From: Sebastian Andrzej Siewior ## DP: Date: Tue, 15 Jun 2010 12:26:38 +0200 ## DP: Subject: [PATCH] Mask a few opcodes on e500 ## DP: ## DP: Backport of http://sourceware.org/ml/binutils-cvs/2010-06/msg00070.html: ## DP: |From: Alan Modra ## DP: |Date: Mon, 14 Jun 2010 14:48:03 +0000 ## DP: |Subject: [PATCH] gas/ ## DP: | * config/tc-ppc.c (md_assemble): Emit APUinfo section for ## DP: | PPC_OPCODE_E500. ## DP: | gas/testsuite/ ## DP: | * gas/ppc/e500.s: Add eieio, mbar and lwsync ## DP: | * gas/ppc/e500.d: Likewise. ## DP: | include/opcode/ ## DP: | * ppc.h (PPC_OPCODE_E500): Define. ## DP: | opcodes/ ## DP: | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and ## DP: | e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 ## DP: | * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which ## DP: | touch floating point regs and are enabled by COM, PPC or PPCCOM. ## DP: | Treat sync as msync on e500. Treat eieio as mbar 1 on e500. ## DP: | Treat lwsync as msync on e500. ## DP: ## DP: mfocrf, mtcrf and mtocrf are not PPCEFS. ## DP: ## DP: Signed-off-by: Sebastian Andrzej Siewior ## DP: --- ## DP: gas/ChangeLog | 5 ++ ## DP: gas/config/tc-ppc.c | 2 +- ## DP: gas/testsuite/ChangeLog | 5 ++ ## DP: gas/testsuite/gas/ppc/e500.d | 5 ++ ## DP: gas/testsuite/gas/ppc/e500.s | 9 +++ ## DP: include/opcode/ChangeLog | 4 + ## DP: include/opcode/ppc.h | 3 + ## DP: opcodes/ChangeLog | 9 +++ ## DP: opcodes/ppc-dis.c | 4 +- ## DP: opcodes/ppc-opc.c | 151 ++++++++++++++++++++++-------------------- ## DP: 10 files changed, 122 insertions(+), 75 deletions(-) if [ $# -ne 1 ]; then echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" exit 1 fi [ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts patch_opts="${patch_opts:--f --no-backup-if-mismatch}" case "$1" in -patch) patch $patch_opts -p1 < $0;; -unpatch) patch $patch_opts -p1 -R < $0;; *) echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" exit 1;; esac exit 0 @DPATCH@ diff --git a/gas/ChangeLog b/gas/ChangeLog index 8e80aaf..9d76754 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2010-06-14 Alan Modra + + * config/tc-ppc.c (md_assemble): Emit APUinfo section for + PPC_OPCODE_E500. + 2010-03-01 Tristan Gingold * config/tc-score7.c (s7_frag_check): Add ATTRIBUTE_UNUSED. diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 7713439..cb4c1e6 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -2897,7 +2897,7 @@ md_assemble (char *str) #ifdef OBJ_ELF /* Do we need/want a APUinfo section? */ - if ((ppc_cpu & PPC_OPCODE_E500MC) != 0) + if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC)) != 0) { /* These are all version "1". */ if (opcode->flags & PPC_OPCODE_SPE) diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 39f9e59..14dd7ea 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2010-06-14 Sebastian Andrzej Siewior + + * gas/ppc/e500.s: Add eieio, mbar and lwsync + * gas/ppc/e500.d: Likewise. + 2010-02-08 Christophe Lyon * gas/arm/branch-reloc.s, gas/arm/branch-reloc.d, diff --git a/gas/testsuite/gas/ppc/e500.d b/gas/testsuite/gas/ppc/e500.d index d338d38..19b17db 100644 --- a/gas/testsuite/gas/ppc/e500.d +++ b/gas/testsuite/gas/ppc/e500.d @@ -49,3 +49,8 @@ Disassembly of section \.text: 9c: 10 a0 22 f7 efdctsf r5,r4 a0: 10 a0 22 f6 efdctuf r5,r4 a4: 10 a0 22 ef efdcfs r5,r4 + a8: 7c 20 06 ac mbar 1 + ac: 7c 00 06 ac mbar + b0: 7c 20 06 ac mbar 1 + b4: 7c 00 04 ac msync + b8: 7c 00 04 ac msync diff --git a/gas/testsuite/gas/ppc/e500.s b/gas/testsuite/gas/ppc/e500.s index e78f251..c506078 100644 --- a/gas/testsuite/gas/ppc/e500.s +++ b/gas/testsuite/gas/ppc/e500.s @@ -45,3 +45,12 @@ start: efdctsf 5,4 efdctuf 5,4 efdcfs 5,4 + + # eieio handling + eieio + mbar + mbar 1 + + #sync and lwsync handling + sync + lwsync diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index fad19ae..620d1e5 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2010-06-14 Sebastian Andrzej Siewior + + * ppc.h (PPC_OPCODE_E500): Define. + 2009-10-02 Peter Bergner * ppc.h (PPC_OPCODE_476): Define. diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index eb8293d..c7e716c 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -173,6 +173,9 @@ extern const int powerpc_num_opcodes; /* Opcode is supported by PowerPC 476 processor. */ #define PPC_OPCODE_476 0x200000000ULL +/* Opcode which is supported by the e500 family */ +#define PPC_OPCODE_E500 0x800000000ULL + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 68ef62c..89664f8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2010-06-14 Sebastian Andrzej Siewior + + * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and + e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 + * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which + touch floating point regs and are enabled by COM, PPC or PPCCOM. + Treat sync as msync on e500. Treat eieio as mbar 1 on e500. + Treat lwsync as msync on e500. + 2010-02-18 Matthew Gretton-Dann * arm-dis.c: Fix mis-applied patch. diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 883bb3b..86aa8fb 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -112,7 +112,7 @@ struct ppc_mopt ppc_opts[] = { { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI - | PPC_OPCODE_E500MC), + | PPC_OPCODE_E500), 0 }, { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI @@ -121,7 +121,7 @@ struct ppc_mopt ppc_opts[] = { { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI - | PPC_OPCODE_E500MC), + | PPC_OPCODE_E500), 0 }, { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 0 }, diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 123436c..9495372 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1776,6 +1776,9 @@ extract_dm (unsigned long insn, /* An XL_MASK with the BO, BI and BB fields fixed. */ #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) +/* An X form mbar instruction with MO field. */ +#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21)) + /* An XO form instruction. */ #define XO(op, xop, oe, rc) \ (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) @@ -1935,6 +1938,7 @@ extract_dm (unsigned long insn, #define PPCRFMCI PPC_OPCODE_RFMCI #define E500MC PPC_OPCODE_E500MC #define PPCA2 PPC_OPCODE_A2 +#define E500 PPC_OPCODE_E500 /* The opcode table. @@ -4395,7 +4399,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, {"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"lfsx", X(31,535), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, +{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, {"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, {"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, @@ -4425,7 +4429,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}}, -{"lfsux", X(31,567), X_MASK, COM, PPCNONE, {FRT, RAS, RB}}, +{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, {"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, @@ -4438,13 +4442,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}}, {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, -{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}}, +{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, +{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}}, +{"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, -{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, +{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}}, @@ -4463,7 +4469,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}}, -{"lfdux", X(31,631), X_MASK, COM, PPCNONE, {FRT, RAS, RB}}, +{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, {"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, @@ -4490,7 +4496,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, {"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, -{"stfsx", X(31,663), X_MASK, COM, PPCNONE, {FRS, RA0, RB}}, +{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, {"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -4509,7 +4515,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, -{"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}}, +{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, {"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, {"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, @@ -4535,7 +4541,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, -{"stfdx", X(31,727), X_MASK, COM, PPCNONE, {FRS, RA0, RB}}, +{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, {"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -4571,7 +4577,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}}, {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, -{"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}}, +{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, @@ -4641,6 +4647,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}}, +{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}}, {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}}, {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}}, @@ -4731,7 +4738,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}}, -{"stfiwx", X(31,983), X_MASK, PPC, PPCNONE, {FRS, RA0, RB}}, +{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, {"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, @@ -4811,21 +4818,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, {"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, -{"lfs", OP(48), OP_MASK, COM, PPCNONE, {FRT, D, RA0}}, +{"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, -{"lfsu", OP(49), OP_MASK, COM, PPCNONE, {FRT, D, RAS}}, +{"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, -{"lfd", OP(50), OP_MASK, COM, PPCNONE, {FRT, D, RA0}}, +{"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, -{"lfdu", OP(51), OP_MASK, COM, PPCNONE, {FRT, D, RAS}}, +{"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, -{"stfs", OP(52), OP_MASK, COM, PPCNONE, {FRS, D, RA0}}, +{"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}}, -{"stfsu", OP(53), OP_MASK, COM, PPCNONE, {FRS, D, RAS}}, +{"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}}, -{"stfd", OP(54), OP_MASK, COM, PPCNONE, {FRS, D, RA0}}, +{"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}}, -{"stfdu", OP(55), OP_MASK, COM, PPCNONE, {FRS, D, RAS}}, +{"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}}, {"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}}, {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, @@ -4845,14 +4852,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, -{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, -{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, +{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, +{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, -{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, -{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, +{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, +{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, -{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, -{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, +{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, +{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}}, {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}}, @@ -4862,25 +4869,25 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, -{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}}, -{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}}, +{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}}, +{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}}, {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, -{"fmsubs", A(59,28,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, -{"fmadds", A(59,29,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fmadds.", A(59,29,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, -{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, -{"fnmadds", A(59,31,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, @@ -5102,7 +5109,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, {"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}}, -{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}}, +{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, @@ -5113,48 +5120,48 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, -{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, -{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, +{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, -{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, +{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, {"fcir", XRC(63,14,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, -{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, +{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, {"fcir.", XRC(63,14,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, -{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, +{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, {"fcirz", XRC(63,15,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, -{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, +{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, {"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, -{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, -{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, -{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, -{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, -{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, -{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}}, {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}}, -{"fsel", A(63,23,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fsel.", A(63,23,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, -{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}}, +{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}}, {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, -{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}}, +{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}}, {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, @@ -5162,27 +5169,27 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, -{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}}, +{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, @@ -5193,8 +5200,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, -{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, -{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, +{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, @@ -5207,8 +5214,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}}, {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}}, -{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, -{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, +{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, @@ -5225,8 +5232,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}}, -{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, -{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, +{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, @@ -5245,8 +5252,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, -{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, -{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, +{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, @@ -5272,17 +5279,17 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, -{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCNONE, {FRT}}, -{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCNONE, {FRT}}, +{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}}, +{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}}, {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, {"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, -{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476, {FLM, FRB}}, +{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, -{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476, {FLM, FRB}}, +{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, -- 1.5.6.5