zeroc-icee (1.2.0-6.1) 10-endian-limits.patch

Summary

 include/IceE/Config.h |   20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

    
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Patch contents

diff -Nur zeroc-icee-1.2.0/include/IceE/Config.h zeroc-icee-1.2.0.new/include/IceE/Config.h
--- zeroc-icee-1.2.0/include/IceE/Config.h	2007-05-10 01:39:59.000000000 +0200
+++ zeroc-icee-1.2.0.new/include/IceE/Config.h	2007-05-12 23:38:57.000000000 +0200
@@ -96,7 +96,16 @@
 // Most CPUs support only one endianness, with the notable exceptions
 // of Itanium (IA64) and MIPS.
 //
-#if defined(__i386)  || defined(_M_IX86)    || defined (__x86_64) || \
+#if defined(HAVE_ENDIAN_H)
+#   include <endian.h>
+#   if __BYTE_ORDER==__LITTLE_ENDIAN
+#      define ICE_LITTLE_ENDIAN
+#   elif __BYTE_ORDER==__BIG_ENDIAN
+#      define ICE_BIG_ENDIAN
+#   else
+#      error "Unknown endian type"
+#   endif
+#elif defined(__i386)  || defined(_M_IX86)    || defined (__x86_64) || \
     defined (_M_ARM) || defined(__MIPSEL__) || defined (__ARMEL__)
 #   define ICE_LITTLE_ENDIAN
 #elif defined(__sparc) || defined(__sparc__) || defined(__hppa) || \
@@ -109,7 +118,14 @@
 //
 // 32 or 64 bit mode?
 //
-#if defined(__linux) && defined(__sparc__)
+#if defined(HAVE_LIMITS_H)
+#   include <limits.h>
+#   if __WORDSIZE == 64
+#      define ICE_64
+#   else
+#      define ICE_32
+#   endif
+#elif defined(__linux) && defined(__sparc__)
 //
 // We are a linux sparc, which forces 32 bit usr land, no matter the architecture
 //